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this is information on a product in full production. may 2014 docid14419 rev 10 1/33 VIPER17 energy saving viperplus: hv switching regulator for flyback converter datasheet - production data figure 1. typical topology features ? 800 v avalanche rugged power section ? pwm operation with frequency jittering for low emi ? operating frequency: ? 60 khz for l type ? 115 khz for h type ? standby power < 30 mw at 265 vac ? limiting current with adjustable set point ? adjustable and accurate overvoltage protection ? on-board soft-start ? safe auto-restart after a fault condition ? hysteresis thermal shutdown applications ? adapters for pda, camcorders, shavers, cellular phones, videogames ? auxiliary power supply for lcd/pdp tv, monitors, audio systems, computer, industrial systems, led driver, no el-cap led driver ? smps for set-top boxes, dvd players and recorders, white goods description the device is an off-line converter with an 800 v rugged power section, a pwm control, two levels of overcurrent protection, overvoltage and overload protections, hysteresis thermal protection, soft-start and safe auto-restart after any fault condition removal. the burst mode operation and the device?s very low consumption meet the standby energy saving regulations. advance frequency jittering reduces emi filter cost. brown-out function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. the high voltage start-up circuit is embedded in the device. so - 16 dip-7 so16 narrow dc input high voltage wide range - + dc output voltage - + VIPER17 drain drain br vdd cont fb gnd table 1. device summary order codes package packaging VIPER17ln / VIPER17hn dip-7 tube VIPER17hd / VIPER17ld so16 narrow tube VIPER17hdtr / VIPER17ldtr tape and reel www.st.com
contents VIPER17 2/33 docid14419 rev 10 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.5 auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.7 current mode conversion with adjustable current limit set point . . . . . . . 19 7.8 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.9 about cont pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.10 feed-back and overload protection (olp) . . . . . . . . . . . . . . . . . . . . . . . . 22 7.11 burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24 7.12 brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.13 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 27 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid14419 rev 10 3/33 VIPER17 block diagram 33 1 block diagram 2 typical power figure 2. block diagram th er mal shutdown 6ua leb & ovp logic soft start ocp block ref tu r n -on logic drain supply & uvlo otp olp burst internal supply bus br burst-mode logic burst s r1 r2 q - + uvlo vin_ok + - ocp ref erence voltages ovp 15ua i ddch ovp vcc oscillator fb v brth hv_on otp . gnd + - rsense cont + - pwm 2nd ocp logic vdd table 2. typical power part number 230 v ac 85-265 v ac adapter (1) open frame (2) adapter (1) open frame (2) VIPER17 9 w 10 w 5 w 6 w 1. typical continuous power in non vent ilated enclosed adapter measured at 50 c ambient. 2. maximum practical continuous pow er in an open frame design at 50 c ambient, with adequate heat sinking.
pin settings VIPER17 4/33 docid14419 rev 10 3 pin settings figure 3. connection diagram (top view) note: the copper area for heat dissipation has to be designed under the drain pins. $0y '5$,1 '5$,1 '5$,1 '5$,1 table 3. pin description pin n. name function dip-7 so16 1 1...2 gnd this pin represents the device ground and the source of the power section. -4n.a. not available for user. this pin is mechanically connected to the controller die pad of the frame. in order to improve the noise immunity, is highly recommended connect it to gnd (pin 1-2). 2 5 vdd supply voltage of the control section. this pin also provides the charging current of the external capacitor during start-up time. 3 6 cont control pin. the following functions can be selected: 1. current limit set point adjustment. the internal set default value of the cycle-by-cycle current limit can be reduced by connecting to ground an external resistor. 2. output voltage monitoring. a voltage exceeding v ovp threshold (see table 8 ) shuts the ic down reducing the device consumption. this function is strobed and digitally filtered for high noise immunity. 47fb control input for duty cycle control. internal current generator provides bias current for loop regulation. a voltage below the threshold v fbbm activates the burst-mode operation. a level close to the threshold v fblin means that we are approaching the cycle-by-cycle over-current set point.
docid14419 rev 10 5/33 VIPER17 pin settings 33 510br brownout protection input with hysteresis. a voltage below the threshold v brth shuts down (not latch) the device and lowers the power consumption. device operation restarts as the voltage exceeds the threshold v brth + v brhyst . it can be connected to ground when not used. 7,8 13...16 drain high voltage drain pin. the built-in high voltage switched start-up bias current is drawn from this pin too. pins connected to the metal frame to facilitate heat dissipation. table 3. pin description (continued) pin n. name function dip-7 so16
electrical data VIPER17 6/33 docid14419 rev 10 4 electrical data 4.1 maximum ratings 4.2 thermal data table 4. absolute maximum ratings symbol pin (dip7) parameter value unit min max v drain 7, 8 drain-to-source (ground) voltage 800 v e av 7, 8 repetitive avalanche energy (limited by t j = 150 c) 2mj i ar 7, 8 repetitive avalanche current (limited by t j = 150 c) 1a i drain 7, 8 pulse drain current 2.5 a v cont 3 control input pin voltage (with i cont = 1 ma) -0.3 self limited v v fb 4 feed-back voltage -0.3 5.5 v v br 5 brown-out input pin voltage (with i br = 0.5 ma) -0.3 self limited v v dd 2 supply voltage (i dd = 25 ma) -0.3 self limited v i dd 2 input current 25 ma p tot power dissipation at t a < 40 c (dip-7) 1 w power dissipation at t a < 60 c (so16n) 1 w t j operating junction temperature range -40 150 c t stg storage temperature -55 150 c esd (hbm) 1 to 8 human body model 4 kv esd (cdm) 1 to 8 charge device model 1.5 kv table 5. thermal data symbol parameter max value so16n max value dip7 unit r thjp thermal resistance junction pin (dissipated power = 1 w) 35 40 c/w r thja thermal resistance junction ambient (dissipated power = 1 w) 90 110 c/w r thja thermal resistance junction ambient (1) (dissipated power = 1 w) 1. when mounted on a standard single side fr4 board with 100 mm 2 (0.155 sq in) of cu (35 m thick) 80 90 c/w
docid14419 rev 10 7/33 VIPER17 electrical data 33 4.3 electrical characteristics (t j = -25 to 125 c, v dd = 14 v (a) ; unless otherwise specified) a. adjust v dd above v ddon start-up threshold before settings to 14 v. table 6. power section symbol parameter test condition min typ max unit v bvdss break-down voltage i drain = 1 ma, v fb = gnd t j = 25 c 800 v i off off state drain current v drain = 640 v v fb = gnd 60 a v drain = 800 v v fb = gnd 75 a r ds(on) drain-source on state resistance i drain = 0.2 a, v fb = 3 v, v br = gnd, t j = 25 c 20 24 i drain = 0.2 a, v fb = 3 v, v br = gnd, t j = 125 c 40 48 c oss effective (energy related) output capacitance v drain = 0 to 640 v 10 pf table 7. supply section symbol parameter test condition min typ max unit voltage v drain _start drain-source start voltage 60 80 100 v i ddch start up charging current v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v -2 -3 -4 ma v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v after fault. -0.4 -0.6 -0.8 ma v dd operating voltage range after turn-on 8.5 23.5 v v ddclamp v dd clamp voltage i dd = 20 ma 23.5 v v ddon v dd start up threshold v drain = 120 v, v br = gnd, v fb = gnd 13 14 15 v v ddoff v dd under voltage shutdown threshold 7.5 8 8.5 v v dd(restart) v dd restart voltage threshold v drain = 120 v, v br = gnd, v fb = gnd 44.55v
electrical data VIPER17 8/33 docid14419 rev 10 current i dd0 operating supply current, not switching v fb = gnd, f sw = 0 khz, v br = gnd, v dd = 10 v 0.9 ma i dd1 operating supply current, switching v drain = 120 v, f sw = 60 khz 1.8 ma v drain = 120 v, f sw = 115 khz 2 ma i dd_fault operating supply current, with protection tripping 400 a i dd_off operating supply current with v dd < vdd_off v dd = 5 v 270 a table 7. supply section (continued) symbol parameter test condition min typ max unit table 8. controller section symbol parameter test condition min typ max unit feed-back pin v fbolp overload shut down threshold 4.5 4.8 5.2 v v fblin linear dynamics upper limit 3.2 3.3 3.4 v v fbbm burst mode threshold voltage falling 0.4 0.45 0.6 v v fbbmhys burst mode hysteresis voltage rising 50 mv i fb feed-back sourced current v fb = 0.3 v -150 -200 -280 ua 3.3 v < v fb < 4.8 v -3 ua r fb(dyn) dynamic resistance v fb < 3.3 v 14 19 k h fb ? v fb / ? i d 4 9 v/a cont pin vcont_l low level clamp voltage i cont = -100 a0.5v vcont_h high level clamp voltage i cont = 1 ma, 5 5.5 6 v current limitation i dlim max drain current limitation (1) v fb = 4 v, i cont = -10 a t j = 25 c 0.38 0.4 0.42 a t ss soft-start time 8.5 ms t on_min minimum turn on time 220 400 480 ns td propagation delay (2) 100 ns t leb leading edge blanking (2) 300 ns i d_bm peak drain current during burst mode v fb = 0.6 v 90 ma
docid14419 rev 10 9/33 VIPER17 electrical data 33 oscillator section f osc VIPER17l v dd = operating voltage range, v fb = 1 v 54 60 66 khz VIPER17h 103 115 127 khz fd modulation depth VIPER17l 4 khz VIPER17h 8 khz fm modulation frequency 250 hz d max maximum duty cycle 70 80 % overcurrent protection (2 nd ocp) i dmax second over current threshold (2) 0.6 a overvoltage protection v ovp overvoltage protection threshold 2.7 3 3.3 v t strobe overvoltage protection strobe time 2.2 s brown out protection v brth brown out threshold voltage falling 0.41 0.45 0.49 v v brhyst voltage hysteresis above v brth 50 mv i brhyst current hysteresis 7 12 a v brclamp clamp voltage i br = 250 a 3 v v dis brown out disable voltage 50 150 mv thermal shutdown t sd thermal shutdown temperature (2) 150 160 c t hyst thermal shutdown hysteresis (2) 30 c 1. i dlim @ v dd lower than 10 v can range between -5% and +15%. 2. specification assured by design, char acterization and statistical correlation. table 8. controller section (continued) symbol parameter test condition min typ max unit
electrical data VIPER17 10/33 docid14419 rev 10 figure 4. minimum turn-on time test circuit figure 5. brown out threshold test circuit figure 6. ovp threshold test circuit note: adjust v dd above v ddon start-up threshold before settings to 14 v 14 v 3.5 v 50 30 v gnd cont fb vdd drain br drain v drain i drain i dlim time time t onmin 90 % 10 % gnd cont fb vdd drain br drain 14 v 2 v 10 k 30 v i brhyst v brth +v brhyst v brth v br i br v dis i brhyst i drain time time time gnd cont fb vdd drain br drain v ovp v cont v drain 14 v 2 v 10 k 30 v time time
docid14419 rev 10 11/33 VIPER17 typical electrical characteristics 33 5 typical electrical characteristics figure 7. current limit vs t j figure 8. switching frequency vs t j figure 9. drain start voltage vs t j figure 10. hfb vs t j figure 11. brown out threshold vs t j figure 12. brown out hysteresis vs t j
typical electrical characteristics VIPER17 12/33 docid14419 rev 10 figure 13. brown out hysteresis current vs t j figure 14. operating supply current (no switching) vs t j figure 15. operating supply current (switching) vs t j figure 16. current limit vs r lim figure 17. power mosfet on-resistance vs t j figure 18. power mosfet break down voltage vs t j
docid14419 rev 10 13/33 VIPER17 typical electrical characteristics 33 figure 19. thermal shutdown t j v dd i drain v ddon time v ddoff v dd(restart) t sd time time t sd -t hyst shut down after over temperature normal operation normal operation
typical circuit VIPER17 14/33 docid14419 rev 10 6 typical circuit figure 20. min-features flyback application figure 21. full-features flyback application opto r5 c6 ac in r3 ac in vout d3 r1 c5 u2 r4 br c4 r6 c3 c1 d1 gnd c2 r2 d2 br cont drain source control vcc fb v dd gnd br cont drain source control vcc fb c3 c2 br vout r2 daux c5 gnd rl r3 rovp rh rlim r6 d2 u2 ac in d3 r1 c6 opto d1 c4 r5 ac in c1 r4 v dd gnd
docid14419 rev 10 15/33 VIPER17 operation descriptions 33 7 operation descriptions VIPER17 is a high-performance low-voltage pwm controller chip with an 800 v, avalanche rugged power section. the controller includes: the oscillator with jittering feature, the start up circuits with soft-start feature, the pwm logic, the current limit circuit with adjustable set point, the second over current circuit, the burst mode management, the brown-out circuit, the uvlo circuit, the auto-restart circuit and the thermal protection circuit. the current limit set-point is set by the cont pin. the burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment. all the fault protections are built in auto restart mode with very low repetition rate to prevent ic's over heating. 7.1 power section and gate driver the power section is implemented with an avalanche ruggedness n-channel mosfet, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. the power section has a bv dss of 800 v min. and a typical r ds(on) of 20 at 25 c. the integrated sensefet structure allows a virtually loss-less current sensing. the gate driver is designed to supply a controlled gate current during both turn-on and turn- off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 7.2 high voltage startup generator the hv current generator is supplied through the drain pin and it is enabled only if the input bulk capacitor voltage is higher than v drain_start threshold, 80 v dc typically. when the hv current generator is on, the i ddch current (3 ma typical value) is delivered to the capacitor on the v dd pin. in case of auto restart mode after a fault event, the i ddch current is reduced to 0.6 ma, in order to have a slow duty cycle during the restart phase. 7.3 power-up and soft-start up if the input voltage rises up till the device start threshold, v drain_start , the v dd voltage begins to grow due to the i ddch current (see table 7 on page 7 ) coming from the internal high voltage start up circuit. if the v dd voltage reaches v ddon threshold (see ta ble 7 o n page 7 ) the power mosfet starts switching and the hv current generator is turned off. see figure 23 on page 17 . the ic is powered by the energy stored in the capacitor on the vdd pin, c vdd , until when the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation.
operation descriptions VIPER17 16/33 docid14419 rev 10 c vdd capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than v ddoff threshold. in fact, a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. the following formula can be used for the v dd capacitor calculation: equation 1 the t ssaux is the time needed for the steady state of the auxiliary voltage. this time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). during the converter start up time, the drain current limitation is progressively increased to the maximum value. in this way the stress on the secondary diode is considerably reduced. it also helps to prevent transformer saturation. the soft-start time lasts 8.5 ms and the feature is implemented for every attempt of start up converter or after a fault. figure 22. i dd current during start-up and burst mode c vdd i ddch t ssaux v ddon v ddoff ? ---------------------------------------- = burst mode normal mode start- up normal mode i ddch (-3 ma) i dd1 i dd0 i dd v fbbm v fb v drain v fbbmhys v fblin v fbolp v dd v ddoff v ddon t t t t
docid14419 rev 10 17/33 VIPER17 operation descriptions 33 figure 23. timing diagram: normal power-up and power-down sequences figure 24. soft-start: timing diagram i dd v dd v drain v ddon time v in v drain_start power-on power-off normal operation regulation is lost here v in < v drain_start hv startup is no more activated v ddoff v dd(restart) i ddch (3ma) time time time t ss ( soft start- up ) steady state v fb v fblin v fbolp i drain i dlim v out delay (olp) t t t
operation descriptions VIPER17 18/33 docid14419 rev 10 7.4 power down operation at converter power down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. the v dd voltage drops and when it falls below the v ddoff threshold (see table 7 on page 7 ) the power mosfet is switched off, the energy transfers to the ic interrupted and consequently the v dd voltages decreases, figure 23 on page 17 . later, if the v in is lower than v drain_start (see table 7 on page 7 ), the start up sequence is inhibited and the power down completed. this feature is useful to prevent converter?s restart attempts and ensures monotonic output voltage decay during the system power down. 7.5 auto restart operation if after a converter power down, the v in is higher than v drain_start, the start up sequence is not inhibited and will be activated only when the v dd voltage drops down the v dd(restart) threshold (see table 7 on page 7 ). this means that the hv start up current generator restarts the v dd capacitor charging only when the v dd voltage drops below v dd(restart) . the scenario above described is for instance a power down because of a fault condition. after a fault condition, the charging current, i ddch , is 0.6 ma (typ.) instead of the 3 ma (typ.) of a normal start up converter phase. this feature together with the low v dd(restart) threshold ensures that, after a fault, the restart attempts of the ic has a very long repetition rate and the converter works safely with extremely low power throughput. the figure 25 shows the ic behavioral after a short circuit event. figure 25. timing diagram: behavior after short circuit 9 '5$,1 6kruwflufxlwrffxuvkhuh w w w w 7 uhs 7 uhs w 9 )% 9 )%ros 9 '' 9 '' rq 9 '' rii 9 '' 9 ''5(67$57 , ''fk p$ 6kruwflufxlwrffxuvkhuh w w w w 7 uhs 7 uhs w 9 )%olq , ''
docid14419 rev 10 19/33 VIPER17 operation descriptions 33 7.6 oscillator the switching frequency is internally fixed to 60 khz or 115 khz. in both case the switching frequency is modulated by approximately 4 khz (60 khz version) or 8 khz (115 khz version) at 250 hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of side- band harmonics having the same energy on the whole but smaller amplitudes. 7.7 current mode conversion with adjustable current limit set point the device is a current mode converter: the drain current is sensed and converted in voltage that is applied to the non inverting pin of the pwm comparator. this voltage is compared with the one on the feed-back pin through a voltage divider on cycle by cycle basis. the VIPER17 has a default current limit value, i dlim , that the designer can adjust according the electrical specification, by the r lim resistor connected to the cont see figure 16 on page 12 . the cont pin has a minimum current sunk needed to activate the i dlim adjustment: without r lim or with high r lim (i.e. 100 k ) the current limit is fixed to the default value (see i dlim , table 8 on page 8 ). 7.8 overvoltage protection (ovp) the VIPER17 has integrated the logic for the monitor of the output voltage using as input signal the voltage v cont during the off time of the power mosfet. this is the time when the voltage from the auxiliary winding tracks the output voltage, through the turn ratio the cont pin has to be connected to the auxiliary winding through the diode d ovp and the resistors r ovp and r lim as shows the figure 27 on page 21 when, during the off time, the voltage v cont exceeds, four consecutive times, the reference voltage v ovp (see table 8 on page 8 ) the overvoltage protection will stop the power mosfet and the converter enters the auto-restart mode. in order to bypass the noise immediately after the turn off of the power mosfet, the voltage v cont is sampled inside a short window after the time t strobe , see table 8 on page 8 and the figure 26 on page 21 . the sampled signal, if higher than v ovp , trigger the internal ovp digital signal and increments the internal counter. the same counter is reset every time the signal ovp is not triggered in one oscillator cycle. referring to the figure 21 , the resistors divider ratio k ovp will be given by: n aux n sec --------------
operation descriptions VIPER17 20/33 docid14419 rev 10 equation 2 equation 3 where: ? v ovp is the ovp threshold (see table 9 on page 8 ) ? v out ovp is the converter output voltage value to activate the ovp (set by designer) ? n aux is the auxiliary winding turns ? n sec is the secondary winding turns ? v dsec is the secondary diode forward voltage ? v daux is the auxiliary diode forward voltage ? r ovp together r lim make the output voltage divider than, fixed r lim, according to the desired i dlim , the r ovp can be calculating by: equation 4 the resistor values will be such that the current sourced and sunk by the cont pin be within the rated capability of the internal clamp. k ovp v ovp n aux n sec -------------- v outovp v dsec + () v daux ? ? -------------------------------------------------------------------------------------------------- - = k ovp r lim r lim r ovp + ---------------------------------- = r ovp r lim 1k ovp ? k ovp ---------------------- - =
docid14419 rev 10 21/33 VIPER17 operation descriptions 33 figure 26. ovp timing diagram 7.9 about cont pin referring to the figure 27 , through the cont pin, the below features can be implemented: 1. current limit set point 2. over voltage protection on the converter output voltage the table 9 on page 22 referring to the figure 27 , lists the external components needed to activate one or plus of the cont pin functions. figure 27. cont pin configuration t v aux t t t strobe t counter reset t counter status t 0 v cont 2 s 0.5 s ovp fault 0 0 0 0 11 22 0 0 11 22 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t v ovp t t t strobe t counter reset t counter status t 0 2 s 0.5 s ovp fault 0 0 0 0 11 22 0 0 11 22 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t + - ovp r ov p soft start cont daux r lim from r sense auxiliary winding to gate driver ovp logic ocp block ocp
operation descriptions VIPER17 22/33 docid14419 rev 10 7.10 feed-back and overload protection (olp) the VIPER17 is a current mode converter: the feedback pin controls the pwm operation, controls the burst mode and actives the overload protection. figure 28 on page 24 and figure 29 show the internal current mode structure. with the feedback pin voltage between v fbbm and v fblin , see table 8 on page 8 , the drain current is sensed and converted in voltage that is applied to the non inverting pin of the pwm comparator. see figure 2 on page 3 . this voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis. when these two voltages are equal, the pwm logic orders the switch off of the power mosfet. the drain current is always limited to i dlim value. in case of overload the feedback pin increases in reaction to this event and when it goes higher than v fblin , the pwm comparator is disabled and the drain current is limited to i dlim by the ocp comparator, see figure 2 on page 3 . when the feedback pin voltage reaches the threshold v fblin an internal current generator starts to charge the feedback capacitor (c fb ) and when the feedback voltage reaches the v fbolp threshold, the converter is turned off and the start up phase is activated with reduced value of i ddch to 0.6 ma. see table 7 on page 7 . during the first start up phase of the converter, after the soft-start up time, t ss , the output voltage could force the feedback pin voltage to rise up to the v fbolp threshold that switches off the converter itself. to avoid this event, the appropriate feedback network has to be selected according to the output load. more the network feedback fixes the compensation loop stability. the figure 28 on page 24 and figure 29 show the two different feedback networks. the time from the over load detection (v fb = v fblin ) to the device shutdown (v fb = v fbolp ) can be calculating by c fb value (see figure 28 on page 24 and figure 29 ), using the formula: equation 5 in the figure 28 , the capacitor connected to fb pin (c fb ) is used as part of the circuit to compensate the feedback loop but also as element to delay the olp shut down owing to the time needed to charge the capacitor (see equation 5). table 9. cont pin configurations function / component r lim (1) 1. r lim has to be fixed before of r ovp r ovp d aux i dlim reduction see figure 16 no no ovp 80 k see equation 4 yes i dlim reduction + ovp see figure 16 see equation 4 yes t olp delay ? c fb v fbolp v fblin ? 3 a --------------------------------------- - =
docid14419 rev 10 23/33 VIPER17 operation descriptions 33 after the start up time, t ss , during which the feedback voltage is fixed at v fblin , the output capacitor could not be at its nominal value and the controller interpreter this situation as an over load condition. in this case, the olp delay helps to avoid an incorrect device shut down during the start up. owing to the above considerations, the olp delay time must be long enough to by-pass the initial output voltage transient and check the over load condition only when the output voltage is in steady state. the output transient time depends from the value of the output capacitor and from the load. when the value of the c fb capacitor calculated for the loop stability is too low and cannot ensure enough olp delay, an alternative compensation network can be used and it is showed in figure 29 on page 24 . using this alternative compensation network, two poles (f pfb , f pfb1 ) and one zero (f zfb ) are introduced by the capacitors c fb and c fb1 and the resistor r fb1 . the capacitor c fb introduces a pole (f pfb ) at higher frequency than f zb and f pfb1 . this pole is usually used to compensate the high frequency zero due to the esr (equivalent series resistor) of the output capacitance of the fly-back converter. the mathematical expressions of these poles and zero frequency, considering the scheme in figure 29 are reported by the equations below: equation 6 equation 7 equation 8 the r fb(dyn) is the dynamic resistance seen by the fb pin. the c fb1 capacitor fixes the olp delay and usually c fb1 results much higher than c fb . the equation 5 can be still used to calculate the olp delay time but c fb1 has to be considered instead of c fb . using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough olp delay time alike. 1 fb 1 fb zfb r c 2 1 f ? ? ? = () 1 fb ) dyn ( fb fb 1 fb ) dyn ( fb pfb r r c 2 r r f ? ? ? ? + = () ) dyn ( fb 1 fb 1 fb 1 pfb r r c 2 1 f + ? ? ? =
operation descriptions VIPER17 24/33 docid14419 rev 10 figure 28. fb pin configuration figure 29. fb pin configuration 7.11 burst-mode operation at no load or very light load when the load decrease the feedback loop reacts lowering the feedback pin voltage. if it falls down the burst mode threshold, v fbbm , the power mosfet is not more allowed to be switched on. after the mosfet stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding the level, v fbbm + v fbbmhys , the power mosfet starts switching again. the burst mode thresholds are reported on table 8 and figure 30 shows this behavior. systems alternates period of time where power mosfet is switching to period of time where power mosfet is not switching; this device working mode is the burst mode. the power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. the advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. during the burst-mode the drain current peak is clamped to the level, i d_bm , reported on table 8 . from sense fet v fbolp burst pwm control cfb to pwm logic burst-mode references burst-mode logic + - pwm + - olp comparator to disable logic v fbolp from r sense pwm control + - pwm burst to disable logic + - olp comparator to gate driver burst-mode logic cfb1 rfb1 cfb burst-mode references
docid14419 rev 10 25/33 VIPER17 operation descriptions 33 figure 30. burst mode timing diagram, light load management 7.12 brown-out protection brown-out protection is a not-latched shutdown function activated when a condition of mains under voltage is detected. the brown-out comparator is internally referenced to v brth threshold, see table 8 on page 8 , and disables the pwm if the voltage applied at the br pin is below this internal reference. under this condition the power mosfet is turned off. until the brown out condition is present, the v dd voltage continuously oscillates between the v ddon and the uvlo thresholds, as shown in the timing diagram of figure 31 on page 26 . a voltage hysteresis is present to improve the noise immunity. the switching operation is restarted as the voltage on the pin is above the reference plus the before said voltage hysteresis. see figure 5 on page 10 . the brown-out comparator is provided also with a current hysteresis, i brhyst . the designer has to set the rectified input voltage above which the power mosfet starts switching after brown out event, v inon , and the rectified input voltage below which the power mosfet is switched off, v inoff . thanks to the i brhyst , see table 8 on page 8 , these two thresholds can be set separately. i drain v fbbm v fb t t 50 mv hyster. burst-mode normal - mode normal - mode t t 50 mv hyster. burst-mode burst-mode normal - mode normal - mode normal - mode normal - mode 100
operation descriptions VIPER17 26/33 docid14419 rev 10 fixed the v inon and the v inoff levels, with reference to figure 31 , the following relationships can be established for the calculation of the resistors r h and r l : equation 9 equation 10 for a proper operation of this function, v in on must be less than the peak voltage at minimum mains and v in off less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. the br pin is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the off threshold when the converter operates or gives origin to undesired switch-off of the device during esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this kind. if the brown-out function is not used the br pin has to be connected to gnd, ensuring that the voltage is lower than the minimum of v dis threshold (50 mv, see tab le 8 ). in order to enable the brown-out function the br pin voltage has to be higher than the maximum of v dis threshold (150 mv, see table 8 ). figure 31. brown-out protection: br external setting and timing diagram rh rl ac_ok disable - + br v dis v in_ok vcc + - v brth i brhyst v in v in v drain v out v br v brth v in_ok i br t t t t t t t v inon v inoff i brhyst t t t t t t t v dd v dd v ddon v ddoff brhyst brth brth ino brhyst ino inon brhyst brhyst l i v v v v v v i v r ? ? ? + ? = brhyst brhyst l l brhyst brhyst inoff inon h i v r r i v v v r + ? ? =
docid14419 rev 10 27/33 VIPER17 operation descriptions 33 7.13 2 nd level overcurrent protection and hiccup mode the VIPER17 is protected against short circuit of the secondary rectifier, short circuit on the secondary winding or a hard-saturation of fly-back transformer. such as anomalous condition is invoked when the drain current exceed the threshold i dmax (see table 8 on page 8 ). to distinguish a real malfunction from a disturbance (e.g. induced during esd tests) a ?warning state? is entered after the first signal trip. if in the subsequent switching cycle the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the i dmax threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power mosfet is turned off. the shutdown condition is latched as long as the device is supplied. while it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the v dd capacitor decays till the v dd under voltage threshold (v ddoff ), which clears the latch. the start up hv current generator is still off, until v dd voltage goes below its restart voltage, v dd(restart) . after this condition the v dd capacitor is charged again by 600 a current, and the converter switching restarts if the v ddon occurs. if the fault condition is not removed the device enters in auto-restart mode. this behavioral results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. see the timing diagram of figure 32 . figure 32. hiccup-mode ocp: timing diagram vcc v drain i drain secondary diode is shorted here t t t dmax on off (restart) secondary diode is shorted here t t t i v dd v dd v dd v dd
package mechanical data VIPER17 28/33 docid14419 rev 10 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 33. dip-7 drawing
docid14419 rev 10 29/33 VIPER17 package mechanical data 33 1- the leads size is comprehensive of the thickness of the leads finishing material. 2- dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3- package outline exclusive of metal burrs dimensions. 4- datum plane ?h? coincident with the bottom of lead, where lead exits body. 5- ref. poa mother doc. 0037880 6- creepage distance > 800 v 7- creepage distance 250 v 8- creepage distance as shown in the 664-1 cei / iec standard. table 10. dip-7 mechanical data dim. mm typ min max a 5,33 a1 0,38 a2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 d 9,27 9,02 10,16 e 7,87 7,62 8,26 e1 6,35 6,10 7,11 e 2,54 ea 7,62 eb 10,92 l 3,30 2,92 3,81 m (6)(8) 2,508 n 0,50 0,40 0,60 n1 0,60 o (7)(8) 0,548
package mechanical data VIPER17 30/33 docid14419 rev 10 figure 34. so16 narrow drawing
docid14419 rev 10 31/33 VIPER17 package mechanical data 33 table 11. so16 narrow mechanical data dimensions ref. databook (mm.) min typ. max a 1.75 a1 0.1 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.8 9.9 10 e 5.866.2 e1 3.8 3.9 4 e 1.27 h 0.25 0.5 l 0.4 1.27 k 0 8 ccc 0.1
revision history VIPER17 32/33 docid14419 rev 10 9 revision history table 12. document revision history date revision changes 14-feb-2008 1 initial release 19-feb-2008 2 updated: figure 1 on page 1 , figure 3 on page 4 21-jul-2008 3 added new so16 package 30-sep-2008 4 updated equation 9 , equation 10 16-jan-2009 5 updated chapter 7.13 on page 27 20-jul-2009 6 updated application paragraph in coverpage and table 8 on page 8 14-jun-2010 7 updated figure 3 on page 4 and table 3 on page 4 23-jul-2013 8 updated table 8: controller section . minor text changes. 30-aug-2013 9 modified the footnote in table 8: controller section . 20-may-2014 10 modified the title and the features in cover page. updated section 3: pin settings , section 4.1: maximum ratings , section 4.3: electrical characteristics . minor text changes.
docid14419 rev 10 33/33 VIPER17 33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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